Memory devices are commonly employed as internal storage areas in computer or processors or other types of electronic equipment. One specific type of memory used to store data in a computer is random access memory (RAM) such as static RAM (SRAM) or dynamic RAM (DRAM). RAM is typically used for example as main memory in a computer. Furthermore random access memory is generally volatile in that once power has been removed the data stored in the memory is lost.
A typical SRAM device includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein which represents a logical data bit in other words a ‘0’ or ‘1’. One known configuration for SRAM cells includes a pair of cross coupled devices such as inverters formed from pairs of complementary metal oxide semiconductor (CMOS) transistors. For example each inverter can be a PMOS FET (p-channel field effect transistor) and a complimentary NMOS FET (n-channel field effect transistor). The inverter is connected in a cross coupled configuration and forms a latch that stores the data as long as the power is maintained to the memory cell. In a conventional six transistor (6T) cell, a pair of access transistors or pass gates (actuated by a word-line WL signal) selectively couples the inverters to a pair of complimentary bit-lines (BL). In other SRAM designs any suitable number of transistors can be implemented such as for example 4T, 8T memory cells.
Designing SRAM cells traditionally involves a compromise between the read and write functions of the memory cell to maintain cell stability, the read performance and the write performance. The transistors which form the cross coupled pair should be weak enough to be overdriven during a write operation while also being strong enough to maintain a data value while driving a bit line during a read operation. The access transistors that connect the cross coupled cell nodes to the true and complement bit lines affect both the stability and performance of the cell. In one port or single port SRAM cells a single pair of access transistors is used for both read and write access to the cell. The gates are driven to a digital value in order to switch the transistors between an on and off the state. The write operation optimisation of the access transistors requires a low on-resistance however the read optimisation requires a high on-resistance to isolate the cell from the bit line capacitance and prevent a cell disturb event.
One proposed approach to improve write performance of SRAM device is to use a ‘negative boost’ to discharge a bit-line to a voltage level below the nominal low supply rail value (for example ground) so that the access transistors of the SRAM cell coupled to the discharge bit-line see a resultant increase in both the gate to source and the drain to source voltages.
However there are problems associated with this technique. For example at high temperatures or voltages or in areas of the integrated circuit where process parameters lead to poor insulation in the FET the application of the ‘negative boost’ or ‘negative bump’ can be detrimental to the reliability of the circuit. For example the ‘negative boost’ effect is generally proportional to temperature as the capacitor used to generate the negative boost is typically a MOSFET capacitor. Furthermore similarly the ‘negative boost’ is proportional to the supply voltage Vdd as the charge stored by the capacitor is increased.
It has been proposed that in order to limit the effects of the ‘negative boost’ write assist operation that diodes can be used to clamp boost applied. However such diode clamps are not effective as they cannot compensate the peak boost voltage generated at high voltage and temperature and this poses serious restrictions on the bump value at lower voltage and temperature.